In the manufacture of integrated-circuit devices, conductive paths or links are typically provided in the form of one or several conductive layers which are patterned by etching in the presence of a mask. In many instances, in the interest of providing for redundancy with respect to device functions for example, it is desirable to include links which can be severed or fused, e.g., depending on the outcome of tests carried out on a device structure. In this respect, and more specifically with respect to complementary metal-oxide-semiconductor (CMOS) devices (see, e.g., U.S. Pat. No. 4,590,388, issued May 20, 1986 to D. G. Clemons et al., entitled "CMOS Spare Decoder Circuit"), conductive paths may be severed by laser irradiation ("laser programming") or else by a suitable electric current pulse through the path. And since, typically, conductive paths have significant cross-sectional area, considerable energy may be required for severing. Even more energy may be required when paths are covered by a dielectric layer; on the other hand, in the absence of such a layer, there is a danger of device impairment due to "splash", as link material removed may be redeposited on a device surface. Moreover, and especially when a dielectric has undergone planarization etching, dielectric thickness may vary across an integrated-circuit device chip, so that the amount of energy needed to sever a link may be ill-determined. As a consequence either too much or too little laser energy may be supplied in an attempt at laser programming--leading to device damage or to incomplete severing of a conductive path.
In view of such and similar considerations it is desirable to provide for specifically selected portions of conductive paths to be more readily severed by laser irradiation or by an electric current pulse.